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anyone familiar with verilog?

quarryman · 2004-07-01 14:42:02

[edit] ....ok i'm gonna simplify the question :) I'm trying to compile and run a simple bit of code that describes some logic gates and need to know how to use VCS in the linux command line to compile it. i know that I am supposed to use vcs followed by the source file and arguments but can't seem to figure it out. is…

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01-07-2004 3:42pm

#1

quarryman

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[edit] ....ok i'm gonna simplify the question

I'm trying to compile and run a simple bit of code that describes some logic gates and need to know how to use VCS in the linux command line to compile it.

i know that I am supposed to use vcs followed by the source file and arguments but can't seem to figure it out.

is there anywhere i can go to get some tutorial help on this?

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#2 06-07-2004 10:40pm
joc_06

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just save your file as xxxxxxxxxxx.v
and then just verilog xxxxxxxxxxx.v

it should compile it and give error report. go to www.deeps.org for a good tut - .df about 5 mb

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