Gate Count

01friel

I'm trying to compare the LMS algorithm with the Fast LMS algorithm by using gate counts,
Need to know gate count for multipliers and adders at 50 MHz

Capt'n Midnight

Gate count depends on how you implement it.
eg: Multiplier based on successive add and shift using carry ripple adders woul d take a fraction of the gates than a multiplier based on parallel carry look ahead adders.

someone might have a link to gate count but as a first approximation...

a N bit carry look ahead adder takes 4 clock cycles (or edges) but about two times ( N squared ) gates. The ripple adder takes something like 4N gates but takes 3+N timings.

same is true of multiplers, you can have successive addition, which takes little more hard ware then the above adders and a shift register or you can have parallel adders which users N-1 times the number of adders above. Again the difference is in the timing, successive addition means a multiplication takes N times as long as an addition where as parallel adding takes about Log2(N) times as long.

So it depends on which type of adders and multipliers you use, also if you are using maths coprocessors then you are looking at a full chip to have all the logarithmic functions.

01friel

Would be interested in the most efficient count, Can't find much info, any links?, tried Xilinx and synopsis but having no joy.