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anyone got any spec's on the AMD Thunderbird

  • 26-05-2000 9:05am
    #1
    Registered Users, Registered Users 2 Posts: 4,109 ✭✭✭


    I'v heard lots about the Duron and nothing on the Thunderbird, It looks to be the Hi MHz one of the two and thats all I know. Will it work with a Athlon Motherboard like the Duron? How much L2 cache dose it have, is it 16 way like the Duron, is it on die...ect


Comments

  • Closed Accounts Posts: 353 ✭✭Yossarian


    Thunderbird will have 256K on die L2 cache,
    it will be available in socket A only to the public. It should work on any socket A motherboard.
    16 way Duron??????? what exactly do you mean by that??

    Stephen




  • Closed Accounts Posts: 6,601 ✭✭✭Kali


    from aceshardware:

    Thunderbird 800 $250
    Thunderbird 850 $330
    Thunderbird 900 $450
    Thunderbird 950 $605
    Thunderbird 1000 $850

    800 for £250 OEM price? whoa.

    http://www.filmsoc.com


  • Registered Users, Registered Users 2 Posts: 4,109 ✭✭✭sutty


    I had read a report on the Duron a wile back and it said (not sure if its true or not but) that a p3's L2 cache can take info on four paths and then send it to the cpu on four paths, the duron can do this on 16 making it do more info in a second, or something like that, Didn't realy understand it but i think that what it was saying is that if you have 256kb of 16 way L2 cache its the same as having 4 times the amount of 256 4 cache.
    or something like that I'm realy not to sure but it sounded kind of cool

    [This message has been edited by sutty (edited 26-05-2000).]


  • Closed Accounts Posts: 353 ✭✭Yossarian


    cant recall anything about the Durons l2 cache, just thought you might have been refering to a 16 processor duron system
    which would have been very interesting.

    what is interesting is the fact that 800Mhz Thunderbirds cost only $250. Could be interesting to see what it overclockes to, as most new cores have a lot of headroom.



  • Registered Users, Registered Users 2 Posts: 4,457 ✭✭✭Gerry


    The amount of ways the cache has is the amount of address lines it has ( I think ) The p3 has 8-way associativity, a 256bit bus, and a latency of 0, making it a rather good cache. 256k cache is 256k cache though, no matter how you look at it. If a program fitted in the 512k cache and not in the 256k cache, it will run slower. No amount of ways will make a 256k cache equivalent to a larger cache, it will just make it a bit more efficient. Thats why the coppermine is slower than the katmai for some things, although this is not widely documented. For most applications it is much faster. The thunderbird will probably not have the same percentage improvement over the athlon as the coppermine had over the katmai p3 because the t-bird and the athlon both have 128kb level1 cache.


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  • Registered Users, Registered Users 2 Posts: 4,151 ✭✭✭_CreeD_


    Gerry, I don't think the coppermine has a Level 1 increase over the Katmai core either. The Athlon's 128 is double that of katmai (and CuMine AFAIK, but Im too lazy too check... smile.gif..).

    I think you're right on the associative side. From what I remember more pipes means greater throughput but higher cache latency. AMDs pre-emptive multi-tasking is statistically superior to Intels so their latency isnt as much of an issue as they make less 'misses'.
    The 256kb on die running at full frequency will be a big boost. The main reason CuMines pulled ahead at the high end was the fact that their cache speed was effectively doubling clock for clock over an equivalent Athlon.

    I havent looked at this stuff in a while, so feel free to blast holes in any of this....So long as ye back it up... wink.gif


  • Closed Accounts Posts: 6,601 ✭✭✭Kali


    athlons dont have 128kb L1, they have 64kb L1.

    the tbird has no increase in L1 over the athlon.

    right onto coppermine:

    katmai and coppermine cores have 16kb data cache + 16Kk instruction cache= 32kb L1 cache.

    the coppermine changed to 256kb on-die L2 from 512kb off-die and increased the data line to that cache (which was one of the main performance increase factors)

    to clear up the "info on four paths" "16 way" confusion/crap .. a 16 way associative cache (found on the tbird) means that every address is mapped to a certain set of cache locations.. the number (16) refers to the number of cache locations in each set.

    hopefully thats cleared some stuff up.



    http://www.filmsoc.com


  • Registered Users, Registered Users 2 Posts: 4,457 ✭✭✭Gerry


    I never said the coppermine had an increase in l1 cache. I really think the athlon does have 128kb l1 cache, consisting of a 64k data cache and a 64k instruction cache. I know the t-bird has no increase in l1 over the athlon. My point was that due to the fact that the athlon and t-bird both have 128kb of ondie l1 cache which is full speed. SO putting an extra 256k of cache on the die would not make as much difference as in the p3's case because it only has 32k l1 cache. ie a lot of stuff would fit in the 128k cache on the athlon.


  • Closed Accounts Posts: 6,601 ✭✭✭Kali


    sorry bout that gerry seems your right bout 128k L1 on the AMDs, very hard to find info on it.
    hell its easier to find specs for the xbox smile.gif

    "and she'll have fun, fun, fun till her daddy takes her tbird away"

    excellent!


    http://www.filmsoc.com


  • Registered Users, Registered Users 2 Posts: 2,518 ✭✭✭Hecate


    any release dates for these processors?


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  • Closed Accounts Posts: 6,601 ✭✭✭Kali


    Duron is set for 4/5th June release,
    Thunderbird (will most likely just be called an Athlon) will be 2/3 weeks after that.
    end of june sometime as they hope to start shipments from the start of the third quarter (july?)

    http://www.filmsoc.com


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